Self-aligned gate and method

ABSTRACT

A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers. Conventional fabrication operations define other structures to complete fabrication of an integrated circuit.

TECHNICAL FIELD

1. The present invention relates generally to semiconductor integratedcircuit processing, and more specifically to an improved method forforming features having critical dimensions, such as transistor gates inan integrated circuit.

BACKGROUND OF THE INVENTION

2. Semiconductor manufacturing is capital intensive and extremelycompetitive. Survival of semiconductor manufacturing concerns depends onconstant innovation to produce more components at lower costs. Newdevice designs often require additional capital investment in order tofabricate the new designs, as is explained below in more detail.

3. The manufacturing cost of an integrated circuit depends in part onhow much semiconductor area is required to implement desired functions.The area, in turn, is defined by geometries and sizes of elements ofactive components such as FET gates and by diffused or implanted regionssuch as FET sources and drains and bipolar transistor emitters andbases.

4. The smallest features in many devices have a critical dimension thatis often similar in size to the wavelengths of light used tophotolithographically define the feature. As a result, further reductionof the size of the critical dimension may require new equipment, usingeither shorter light wavelengths or techniques not dependent on lightfor feature definition (e.g., using focused electron beams). Capitalcosts of several tens of million dollars each are not unusual for thesetypes of equipment.

5. Maximum operating frequency is a figure of merit for integratedcircuits and is determined by a confluence of factors. Parasiticcapacitance in transistors making up the integrated circuits stronglyaffects maximum operating frequency. Higher operating frequencies alsotend to require smaller feature sizes for a variety of reasons. As aresult, design techniques that reduce parasitic capacitance or thatresult in smaller feature sizes can be extremely valuable tosemiconductor manufacturers.

SUMMARY OF THE INVENTION

6. The present invention is directed toward methods of makingtransistors on integrated circuits and transistors and integratedcircuits made using such methods. One method includes forming one ormore layers, which may be dielectric layers, on a surface of asemiconductor substrate that includes planar isolation structures thatwere previously formed on the surface of the semiconductor wafer.Openings having a first width are formed through a top one of the seriesof layers and a blanket dielectric layer having a predeterminedthickness is formed in the openings and on the series of layers. Ananisotropic etch removes the blanket dielectric layer from the series oflayers and from bottoms of the openings but not from sidewalls of theopenings, thereby forming dielectric spacers. As a result, a gap betweenthe dielectric spacers has a second width that is equal to the firstwidth minus twice the thickness of the blanket dielectric layer.

7. A first ion implantation through the gaps defines channels fortransistors. In one aspect, the present invention employs an angledfirst ion implantation to provide a “halo” of implanted ions extendingunder at least one spacer at one edge of each of the gaps. In anotheraspect, the present invention employs a first ion implantation at normalor near normal incidence through the gaps. A gate material, which mayinclude polycrystalline silicon, is formed in the gaps and on the seriesof layers. Chemical-mechanical polishing removes the gate material fromthe series of layers, leaving gate material forming a gate in each ofthe gaps. The series of layers that defined the openings aresequentially removed using one or more directional etching processes,leaving the dielectric spacers that were formed from the blanketdielectric layer on the sidewalls of the openings around the gates. Asecond ion implantation forms a source and a drain to either side ofeach gate. Conventional processing then completes FETs forming theintegrated circuit through fabrication of self-aligned silicidecontacts, pre-metal dielectric layers and metallized inter-levelcontacts.

8. As a result, a gate width is realized that is smaller than the firstwidth of the opening by an amount that is equal to twice the thicknessof the blanket dielectric layer. The implanted channel is self-alignedto the gate, reducing processing complexity. The source and drainimplants are also self-aligned with respect to the gates and result inreduced capacitance, increasing operating frequency for the FETs.

BRIEF DESCRIPTION OF THE DRAWINGS

9.FIG. 1 is a flowchart of a process for making a semiconductor device,in accordance with embodiments of the present invention.

10.FIG. 2 is a side cross-sectional view of a portion of a semiconductordevice partway through processing, in accordance with embodiments of thepresent invention.

11.FIG. 3 is a side cross-sectional view of the portion of thesemiconductor device further along in processing, according toembodiments of the present invention.

12.FIG. 4 is a side cross-sectional view of the portion of thesemiconductor device further along in processing, according toembodiments of the present invention.

13.FIG. 5 is a side cross-sectional view of the portion of thesemiconductor device further along in processing, according toembodiments of the present invention.

14.FIG. 6 is a side cross-sectional view of the portion of thesemiconductor device further along in processing, according toembodiments of the present invention.

15.FIG. 7 is a side cross-sectional view of the portion of thesemiconductor device further along in processing, according toembodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

16. The embodiments of the present invention can be practiced inconjunction with conventional integrated circuit fabrication techniques,and therefore, only those process steps necessary for an understandingof the present invention are described. Furthermore, the figuresrepresenting cross-sections of portions of an integrated circuit duringfabrication are not drawn to scale.

17. Referring now to FIGS. 1 and 2, a first part of an embodiment of thepresent invention will now be described in detail. FIG. 1 is a flowchartof a process 25 for carrying out integrated circuit manufacturing, inaccordance with embodiments of the present invention. A substrate 36(FIG. 2) has previously been conventionally processed to provideisolation structures. The substrate 36 has a first type of conductivitythat may be either n- or p-type conductivity, with the wells 38 having asecond type of conductivity different than the first type ofconductivity. In one embodiment, the substrate 36 is a n-type siliconsubstrate 36 and includes p-wells 38. In one embodiment, the substrate36 also includes planar isolation structures, such as conventionalshallow isolation trench structures 39 that include a dielectric formedin a trench in a surface 40 of the substrate 36.

18. Shallow isolation trench structures 39 provide coplanar surfaces 40,forming a benign environment for fine-line lithography. Additionally,shallow isolation trench structures 39 allow active devices to be packedmore densely because the shallow isolation trench structures 39 do notneed the separations between active devices that are required for otherisolation techniques. Other processes that can provide isolationtogether with planar surfaces 40 include selective epitaxial growth andconventional silicon-on-insulator (SOI).

19. Selective epitaxial growth may be carried out by forming an oxidelayer on the substrate 36 and then etching portions of the oxide layeroff of the substrate 36. Epitaxy then results in islands ofsemiconductor material, such as silicon, in the areas where the portionsof the oxide layer were removed. Conventional chemical-mechanicalpolishing then results in a planar surface 40 with isolated regions ofepitaxially grown semiconductor material for active device fabrication.

20. In a step 42, an optional first layer 44 is formed on the surface 40of the substrate 36. In one embodiment, the first layer 44 is formed asa thermal oxide layer grown on the surface 40 of the substrate 36.Thermal oxides are conventionally grown on silicon substrates 36 byheating the substrate 36 to a temperature on the order of 1,000° C. inan oxygen-bearing ambient. In one embodiment, the first layer 44 isformed to have a thickness of about two hundred Angstroms or less,although a greater thickness could be employed. The first layer 44serves to protect the surface 40 from contamination.

21. In a step 46, a second layer 48 is formed on the first layer 44. Thesecond layer 48 is formed from a material that is chemically differentthan the first layer 42. As a result, the second layer 48 may be etchedby an etching process that does not etch the first layer 42. The shallowtrench isolation structures 39 are protected from etching processes thatcould damage or affect them by chemical selectivity with respect to thesecond layer 48, i.e., etching processes for structures formed on thesecond layer 48 are chosen to not be able to etch the second layer 48,thereby shielding structures below the second layer 48 from theseetching processes.

22. In one embodiment, the second layer 48 is formed from siliconnitride that may be deposited by conventional low-pressure chemicalvapor deposition (LPCVD). However, plasma enhanced chemical vapordeposition (PECVD), chemical vapor deposition (CVD) or otherconventional processes may be employed. The thickness of the secondlayer 48 is typically more than 5 Angstroms and thicknesses in a rangeof 200-500 Angstroms or less are desirable, although thicknesses of upto a thousand Angstroms or more may be practical.

23. In a step 50, a third layer 52 is formed on the second layer 48. Thethird layer 52 is formed from a material that is chemically differentthan the second layer 48. As a result, the third layer 52 may be etchedby an etching process that does not etch the second layer 48. In oneembodiment, the third layer 52 is a silicon dioxide layer formed by aPECVD process. In other embodiments, TEOS, LPCVD or atmospheric pressureCVD may be employed to form the third layer 52. The third layer 52 isformed to have a thickness 53 that is tailored to requirements imposedon thickness of a gate, as is described in more detail below. Typicalthicknesses are in a range of several hundred to several thousandAngstroms. The steps 42, 46 and 50 result in the structure shown in FIG.2.

24. In a step 54, openings 56 (FIG. 3) are etched through the thirdlayer 52 to the second layer 48. In one embodiment, the openings 56 areetched using an anisotropic reactive ion etching process that results invertical or nearly vertical sidewalls 58 in the openings 56. The term“anisotropic etching” refers to an etching process that etches much morerapidly in a direction normal to the surface 40 than in otherdirections.

25. Additionally, in one embodiment, the second layer 48 is used as anetch stop in the step 54, i.e., the anisotropic etch is also selectivelyable to etch the third layer 52 but not the second layer 48. In oneembodiment, the openings 56 are etched through openings in photoresist(not shown) that are defined photolithographically using deepultraviolet exposure techniques, although X-ray or electron beamexposure techniques are also possible. In one embodiment, the openings56 have a first width 62 on the order of 200 nanometers. In oneembodiment, the thickness 53 of the third layer 52 is between 100 and500 nanometers.

26. In a step 64, a blanket dielectric layer 66 (FIG. 4) having apredetermined thickness 68 is formed in the openings 56 and on the thirdlayer 52. In one embodiment, the blanket dielectric layer 66 is asilicon nitride layer formed as described above with respect to the step46. As a result, portions of both the second layer 48 and the blanketdielectric layer 66 may be etched during the same etching step, withoutetching the first layer 44 or the shallow trench isolation structures39. In one embodiment, the blanket dielectric layer 66 is a siliconnitride layer providing thicknesses 68 of 50 nanometers on the sidewalls58 of the openings 56. The blanket dielectric layer 66 may be formed byany process that provides good step coverage, such as LPCVD, and thatresults in a blanket dielectric layer 66 that does not react with metalsused in forming self-aligned silicide contacts.

27. In a step 70, the blanket dielectric layer 66 is anisotropicallyetched from bottoms 72 of the openings 56 and from the third layer 52but not from the sidewalls 58 to form dielectric spacers 74 (FIG. 5). Agap 76 between the dielectric spacers 74 thus has a second width 78 thatis equal to the first width 62 minus twice the thickness 68. In oneembodiment, the second width 78 is about 100 nanometers. In oneembodiment, in the step 70, the first layer 44 is used as an etch stop,i.e., the anisotropic etch chosen to etch the second layer 48 and theblanket dielectric layer 66 cannot etch the first layer 44 or the thirdlayer 52.

28. In a step 80, ion implantation and annealing forms a self-alignedchannel 81 (FIG. 6) in the substrate 36 beneath the gap 76. In oneembodiment, the self-aligned channel 81 is formed by implanting atmultiple angles to provide “halos” or “pockets” of implanted ions underthe dielectric spacers 74 on each side of the openings 56 but not in thegaps 76 between the dielectric spacers 74 within the openings 56. Inanother embodiment, the step 80 includes ion implantation at normal ornear-normal incidence to provide the self-aligned channel 81. In oneembodiment, the step 80 also includes implantation forming the wells 38.Following implantation, the implanted ions are activated by conventionalannealing, which may be carried out using rapid thermal annealing oroven baking.

29. In a step 82, a pre-gate cleaning including etching of the firstlayer 44 is carried out and a gate oxide 83 is grown in the gaps 76. Ina step 84, a gate material 86, which may include polycrystallinesilicon, is formed in the openings 56 and on the third layer 52. In astep 88, conventional chemical-mechanical polishing removes the gatematerial 86 from the third layer 52, forming gates 90 in the gaps 76.The gates 90 thus have the second width 78, i.e. a critical dimensionwhich is smaller than the dimension of any conventionally definedfeature on the substrate 36. The openings 56 created in the step 54,together with the dielectric spacers 74 created in the steps 64 and 70,correspond to inverse or negative images that become the gates 90 in thestep 88. The second width 78 of the gaps 76 thus defines the criticaldimension. It will be appreciated that the gates 90 have a dimensiontransverse to the page of the illustrations that is much larger than thesecond width 78.

30. In a step 92, the first 44, second 48 and third 52 dielectriclayers, but not the dielectric spacers 74, are sequentially removedusing a series of etching processes, leaving the dielectric spacers 74that were formed on the sidewalls 58 of the openings 56 around the gates90. In one embodiment, the etching process used to remove the secondlayer 48 in the step 92 is an anisotropic etching process.

31. In a step 94, a second ion implantation and annealing forms source96 (FIG. 7) and drain 98 regions to either side of the gates 90. Theannealing is described above with respect to the step 80. The annealingof the implants of the steps 80 and 94 may be carried out separately inone embodiment or may be combined into a single annealing processfollowing the ion implantation of the steps 80 and 94 in anotherembodiment. In a step 96, conventional self-aligned metal silicidecontacts 102, also known as “salicide” contacts 102, are formed.

32. In one embodiment, the self-aligned silicide contacts 102 are formedby deposition of a metal such as cobalt or titanium that is then reactedwith silicon, e.g., by rapid thermal annealing, to form metal silicidecontacts 102 at top surfaces of the gates 90 and the source 96 and drain98 regions, but the deposited metal does not react with the materialforming the dielectric spacers 74. The metal on the dielectric spacers74 then may be removed using an etching process that does not attack theself-aligned silicide contacts 102, leaving the self-aligned silicidecontacts 102.

33. In a step 104, conventional fabrication processes provide andpattern pre-metal dielectric layers 106. In a step 108, conventionalmetallized inter-level contacts 110 are fabricated, using tungsten,copper or aluminum, for example. The process 25 then ends andconventional processing, packaging and testing operations are carriedout to provide completed FETs 112 and integrated circuits 114 using theFETs 112.

34. The process 25 results in self-aligned gate 90, source 96 and drain98 regions having reduced capacitance in the FETs 112. Capacitancebetween source 96 and drain 98 regions and the substrate 36 is reduced,resulting in improved performance and in particular resulting inincreased operating speed/frequency. In one embodiment, the gates 90have the second width 78 that may be one-half of the first width 62 ofthe openings that were created using lithographic techniques, allowinglithographic tools to be used that were only intended to be able toprovide critical dimensions the size of the first width 62. As a result,lithography tools are provided with a longer useful life, allowingdeferral of investment in capital equipment while still providingreduction in effective gate length.

35. Also, FETs 112 are provided having reduced length for the gate 90(the second width 78 corresponds to gate length) together withself-aligned implanted channels 81 and source 96 and drain 98 regions.As a result, the FETs 112 provide increased operating frequency due toboth reduced capacitance and reduced gate length. The integratedcircuits 114 including the FETs 112 resulting from the process 25provide enhanced performance without requiring increased investment incapital resources.

36. An advantage to the process 25 of FIG. 1 is that the gate oxide 83is formed after all of the steps 42-80. Gate oxides 83 for FETs 112having gate lengths 78 of 100 nanometers are extremely thin, on theorder of fifteen to thirty Angstroms, and are susceptible to damage fromprocessing needed for forming other portions of the integrated circuit114. The process 25 forms the gate oxide 83 in the step 82, immediatelyprior to deposition of the gate material 86 in the step 84. As a result,the gate oxide 83 is not exposed to deposition and subsequent removal ofother layers or structures, avoiding potential contamination or damagethat could occur during the processing for the other layers orstructures.

37. From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A semiconductor structure formed by a method comprising: forming alayer on a surface of a silicon substrate having a first thickness;forming an opening having a first width through the layer; forming ablanket dielectric layer having a second thickness on the layer and inthe opening, the second thickness being less than the first thickness;removing the blanket dielectric layer from the layer and bottom of theopening, but not from sidewalls of the opening, to form dielectricspacers on each side wall within the opening, the gap having a secondwidth less than the first width; depositing a gate electrode into thegap; removing the layer and leaving the dielectric spacers on thesubstrate; and forming source and drain regions adjacent the gateelectrode.
 2. The semiconductor structure of claim 1 , furthercomprising, prior to forming the gate electrode in the gap, implantingions through the gap using a tilted ion beam to produce a halo ofimplanted ions under at least one side of the gap.
 3. The semiconductorstructure of claim 1 , further comprising, prior to forming the gateelectrode in the gap, implanting ions through the gap using a normallyincident or nearly normally incident ion beam.
 4. The semiconductorstructure of claim 1 wherein forming the gate electrode comprises:pre-gate cleaning; forming a gate dielectric on bottom of the gap;forming a layer of conductive material on the layer and on the gatedielectric; and chemical-mechanical polishing to remove the layer ofconductive material from the layer but not from the bottom of the gap.5. The semiconductor structure of claim 1 , further comprising forming aself-aligned metal silicide contact to the gate and to the source anddrain regions.
 6. The semiconductor structure of claim 1 , wherein thelayer is a series of chemically distinct layers formed by the methodcomprising: forming a layer of silicon nitride on the surface of thesubstrate; and depositing an oxide layer on the silicon nitride layer,the deposited oxide layer having a thickness in a range of between 100and 500 nanometers.
 7. The semiconductor structure of claim 1 , whereinforming an opening through the top one of the series of layers includesreactive ion etching the top one of the layers using an anisotropic etchthat does not etch a chemically distinct layer beneath the top one ofthe series of layers.
 8. An integrated circuit including field effecttransistors formed by a method comprising: forming a layer of siliconnitride on a substrate; depositing an oxide layer on the silicon nitridelayer, the oxide layer having a first thickness; forming an openinghaving a first width through the oxide layer; forming a blanketdielectric layer having a second thickness on the oxide layer and in theopenings, the second thickness being half or less of the firstthickness; removing the blanket dielectric layer from the oxide layerand bottoms of the openings but not from sidewalls of the openings toform dielectric spacers on either side of gaps within the openings, thegaps having a second width less than the first width; forming gates ineach of the gaps; removing the oxide layer and the silicon nitride layerbut not the dielectric spacers; and forming source and drain regions. 9.The integrated circuit of claim 8 , further comprising, prior to forminggates in each of the gaps, implanting ions through the gaps using atilted ion beam to produce a halo of implanted ions under at least oneside of the gaps.
 10. The integrated circuit of claim 8 , furthercomprising, prior to forming gates in each of the gaps, implanting ionsthrough the gaps using a normally incident or nearly normally incidention beam.
 11. The integrated circuit of claim 8 wherein forming gatescomprises: pre-gate cleaning; forming a gate dielectric on bottoms ofthe gaps; forming a layer of conductive material on the oxide layer andon the gate dielectric; and chemical-mechanical polishing to remove thelayer of conductive material from the oxide layer.
 12. The integratedcircuit of claim 8 , further comprising forming self-aligned metalsilicide contacts to the gates and to the source and drain regions. 13.The integrated circuit of claim 8 , wherein forming an opening throughthe oxide layer includes reactive ion etching the oxide layer using ananisotropic etch that does not etch the silicon nitride layer beneaththe oxide layer, where the opening has substantially vertical sidewalls.14. A method of forming a feature having a critical dimensioncomprising: forming a first layer having a first thickness; forming anopening having vertical sidewalls separated by a width greater than thecritical dimension extending through the first layer; forming a blanketdielectric layer having a second thickness in the opening, on the firstlayer and on the sidewalls, the second thickness being half or less ofthe first thickness; selectively and anisotropically etching the blanketdielectric layer to form dielectric spacers on the sidewalls and toremove the blanket dielectric layer from a bottom of the opening withoutetching the first layer, the dielectric spacers separated by a gaphaving a width equal to the critical dimension; forming a second layerin the gap and on the first layer; removing those portions of the secondlayer formed on the first layer using a chemical-mechanical polishwithout removing portions of the second layer in the gaps; and removingthe first layer but not the dielectric spacers.
 15. The method of claim14 wherein forming a first layer comprises forming a series ofchemically distinct layers on the surface of the substrate, a top one ofthe series of layers having the first thickness, the first thicknessbeing five thousand Angstroms or less.
 16. The method of claim 14wherein forming a first layer comprises: forming a thermal oxide on thesubstrate, the substrate formed from silicon; forming a silicon nitridelayer having a thickness of less than five hundred Angstroms on thethermal oxide; and forming a silicon dioxide layer having the firstthickness on the silicon nitride layer, the first thickness being fivethousand Angstroms or less.
 17. The method of claim 14 wherein forming ablanket dielectric layer comprises forming a blanket dielectric layer ofsilicon nitride.
 18. The method of claim 14 wherein forming a blanketdielectric layer comprises forming a blanket dielectric layer of siliconnitride using LPCVD.
 19. The method of claim 14 , wherein the substratecomprises silicon and forming a second layer in the gap and on the firstlayer comprises: pre-gate cleaning; thermally growing a gate oxide onthe substrate within the gap; forming a channel within the gap; formingthe second layer of conductive material; and chemical-mechanicalpolishing to remove the second layer from the first layer.
 20. Themethod of claim 14 wherein forming the second layer comprises formingthe second layer of polycrystalline silicon.